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Altium Designer Engineer Assistant

Professional Updated 2026.08.30

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About this skill

Problem

Altium Designer workflows have many commands and rule interactions, so footprint synchronization, polygon pours, DRC, and manufacturing output often require repeated trial and error. This skill organizes the official Altium Designer Day1-Day3 training and custom pad guide into searchable engineering instructions, useful for questions such as where a command is located, what order to run a design step, and what to check first after an error.

Core capabilities and key steps

  • Schematic design: create sheets, place parts, wire nets, define buses, use smart paste with Ctrl+Shift+V, compile projects, and annotate components.
  • Library editing: schematic libraries, PCB footprint libraries, IPC Footprint Wizard, integrated libraries, DBLib, and generating custom pad areas from mechanical outlines.
  • PCB design: layer stack management, design synchronization, placement, interactive routing, differential pairs, length tuning, teardrops, and via handling.
  • Copper and split planes: Polygon Plane, cutouts, slicing, Rebuild Planes, and Split Plane DRC checks for broken planes, dead copper, and starved thermals.
  • 3D, rules, and output: STEP import/export, design rules, DRC, Gerber, NC Drill, ODB++, BOM, SmartPDF, and assembly variants.
  • Advanced scenarios: hierarchical multi-channel reuse, FPGA OpenBus design, FPGA-to-PCB project conversion, and pin swapping.

Boundaries and cautions

This skill is best for Altium Designer workflow guidance and common error triage; it does not replace project-specific electrical rules, library quality, or factory manufacturing standards. When missing footprints, pin mismatches, or disconnected pours appear, check Pin Map, library installation, Connect to Net, Pour Over options, and keep-out constraints first.

Use Cases

  • Configure layer stacks, synchronize schematics, and fix missing footprint errors on a 4-layer board.
  • Troubleshoot unconnected polygon pours by checking split planes, starved thermals, and DRC violations.
  • Generate Gerber, NC Drill, BOM, and assembly variants before manufacturing handoff.
  • Build an FPGA minimum system from OpenBus constraints through FPGA-to-PCB conversion.

Best For

  • Hardware engineers maintaining schematics and footprints who need library editing and multi-part rules.
  • PCB engineers handling layout and routing, differential pairs, vias, and DRC spacing conflicts.
  • Hardware engineers preparing manufacturing handoffs who must verify Gerber, NC Drill, and BOM output.
  • Junior engineers learning Altium workflows who need quick access to shortcuts and command paths.