In the chip frontend design flow, coding agents are responsible for generating RTL and UVM testbenches, but they often lack mechanisms to interact with EDA tools and manage workflows. Developers need a way to enable agents to do more than write code—they should be able to run flows such as simulation, synthesis, and timing analysis, and fix issues based on the results. VeriPower solves this problem.

What Is VeriPower

VeriPower is an open-source plugin maintained by chipweaver, designed to assist frontend chip design and verification flows. It connects coding agents with EDA tools, covering the entire flow from specification, RTL, and lint/CDC to simulation, synthesis, timing analysis, and sign-off.

Core Features

The plugin provides the following capabilities:

  1. Code development: The coding agent develops RTL code and UVM testbenches.
  2. EDA tool execution: Invokes and runs EDA tool chains.
  3. Flow management: Manages cross-stage workflows and records which steps pass and which need to be rerun.
  4. Result checks: Automatically checks coverage, timing, and power metrics.

Installation and Enablement

This plugin must be installed under the web profile of DeepSeek Harness. Please use the following command:

dsh plugin --profile web add "veripower@git+https://github.com/chipweaver/veripower.git"

After installation, make sure to run the dsh web command, not the headless profile.

Typical Usage

After installation, you can use it with the following steps:

  1. Verify installation: Ask the agent to list its skills. A confirmed list of twelve VeriPower skills indicates that the installation was successful.
  2. Clarify requirements: First run the brainstorm skill to establish the requirements.
  3. Run the flow: After the requirements are confirmed, instruct the agent to run the flow for a specified module, for example: “Run the design flow for {module_dir}”.

Environment Requirements

Running VeriPower requires the following conditions:

  • Python: 3.10 or higher.
  • Library dependencies: jsonschema >= 4.18, referencing, PyYAML.
  • EDA tools: Synopsys EDA tools, with support for per-skill replacement.

Conclusion

VeriPower provides a closed-loop flow from specification to sign-off, helping developers use AI assistance to manage tedious EDA workflows. For more details, refer to the plugin directory or the GitHub repository.